1. Field of the Invention
The present invention relates to a liquid crystal television interlacing a liquid crystal display panel of matrix drive.
2. Description of the Prior Art
In a liquid crystal TV with TFT (thin-film transistor) and LCD (liquid crystal display) combined therefor, normally gate lines of TFT are scanned in sequence by a gate driver, and a television signal (amplified to a voltage ready for driving liquid crystal) synchronized with the scanning timing is fed to a source line to TV display.
In case then the television signal is that of NTSC (National TV System Committee) color television system, 525 scanning lines are divided into odd lines (full line) and even lines (chain line) as shown in FIG. 4, and 2:1 interlacing scanning is carried out on every other line to form one picture. Accordingly, in the case of interlacing scanning system, TFT gate drivers 1a, 1b are divided into two groups, one driving gate lines (G.sub.1, G.sub.3, . . . ) of odd number, while the other driving gate lines (G.sub.2, G.sub.4, . . . of even number. Then, the aforementioned interlacing scanning is realized by driving the gate drivers 1a, 1b alternately at every fields in the television signal of NTSC system, that is, at every odd field and even field.
Here, if an odd field picture and an even field picture are not positioned synchronously with each other, there takes place a vertical aberration in picture. The following refers briefly to the reason.
FIG. 6 is a waveform drawing indicating a timing of NTSC composite signal (signal combining chrominance signal, luminance signal and synchronizing signal) with each signal. In the drawing, STV , STV.sub.2 denote start data signals of shift register in the foregoing gate drivers 1a, 1b respectively, CPV.sub.1, CPV.sub.2 denote shift clocks of shift register in the gate drivers 1a, 1b respectively, CLR.sub.1, CLR.sub.2 , denote data reset signals of the gate drivers 1a, 1b, whereby all outputs come to a reset state at the time of "H" (high level). Then, the gate drivers 1a, 1b are controlled on the data reset signals CLR.sub.1, CLR.sub.2, the odd gate driver 1a is driven when CLR.sub.1 ="L" (low level) and CLR.sub.2 ="H", the even gate driver 1b is then kept off in this case, and some odd field is displayed. Then in the next even field, CLR.sub.1 ="H" and CLR.sub.2 ="L" , the odd gate driver 1a is kept off in this case, and the even gate driver 1b is driven. Thus, a display at every fields is given by driving the gate drivers 1a, 1b of the odd gate line and the even gate line alternately, thereby subjecting LCD panel to 2:1 interlacing drive.
In this case, if the aforementioned data reset signals CLR.sub.1, CLR.sub.2 are generated by dividing a vertical synchronizing pulse double, then there may occur CASE 1 (CLR.sub.1, CLR.sub.2) and CASE 2 (CLR.sub.1 ', CLR.sub.2 '), as shown in FIG. 6. For example, if the aforementioned signals are generated on a circuit using a flip-flop 3 and an inverter 4 shown in FIG. 7, there may be a case where signals of CASE 1 and CASE 2 are generated when a power is closed or the composite signal is changed (channel selection). In CASE 1, the odd gate driver 1a is driven, while the even gate driver 1b comes off at the time of odd field timing as shown in FIG. 8, and the even gate driver 1b is driven, while the odd gate driver 1a comes off at the time of even field timing, therefore a video picture according to a transmitted video signal can be reproduced without aberration as shown in FIG. 9 (a) However, in CASE 2, the operation is reversed, and as shown in FIG. 9 (b), there arises an aberration vertically of the displayed picture. In this case, 294 line and 32 line, for example, are shifted each other at the time of horizontal bar signal as shown in FIG. 10, thus displaying an awkward picture.
The prior art liquid crystal TV is constructed as described above, and in the case of interlacing drive, a vertical synchronizing pulse is divided double, thereby obtaining a data reset signal of the gate drivers. Consequently, there occur CASE 1 and CASE 2 as described, each gate driver cannot be driven on video signals of the odd field and the even field, and thus an aberration arises inevitably in a displayed picture.